A pixel driving circuit of an AMOLED (Active Matrix/Organic Light Emitting Diode panel) display usually adopts a TFT (Thin Film Field Effect Transistor), which acts as a driving OLED (Organic Light-Emitting Diode) or PLED (polymer light-emitting diode) panel. Compared to amorphous silicon, the concentration of the carrier of the TFT is ten times as large as that of amorphous silicon. In addition, the TFT can be fabricated by a sputtering method, and thus when the TFT is introduced, the production line of the existing liquid crystal panel need not to be changed to a great extent. Meantime, in the absence of ion implantation and laser crystallization equipment limitations, compared to polysilicon technology, it is more useful for the production of a glass backplate having a large area.
The pixel driving circuit contains two TFTs and a storage capacitor, where one TFT is a switching TFT, and another is a driving TFT. At the time of the activation of a scanning line, a certain voltage is applied to the gate of the switching TFT, and a current flows from the gate to the drain and is transmitted to the driving TFT through an ITO (Indium Tin Oxide) layer to turn on the driving TFT. The current flows from the gate to the drain while the driving TFT is connected with the storage capacitor, thus charging the capacitor. When the scanning line is turned off, the voltage stored in the capacitor can still keep the driving TFT in on state, and thus can maintain a fixed current of the OLED within a picture.
Since the switching TFT and the driving TFT are in different layers, the jump layer connection technique of the switching TFT and the driving TFT is a key technique. Currently, the following two modes are mainly used:
Mode 1: as shown in FIG. 1-1˜FIG. 1-7, there is included mainly the following procedure: The gate metals 101 of the switching TFT and the driving TFT are deposited on a glass substrate and are etched, and a gate insulation (GI) layer 102 is deposited, to form a cross section diagram shown in FIG. 1-1;
An Indium Gallium Zinc Oxide (IGZO) layer 103 is deposited at the position of the switching TFT on the GI layer 102. By etching the IGZO layer 103 by using wet etching, and then depositing ESL (etching stop layer) layer 104 and etching, a cross section diagram shown in FIG. 1-2 is formed;
By using a dry etching technique, the GI layer 102 on the Gate metal 101 of the driving TFT is split to form a cross section diagram shown in FIG. 1-3, and the source/drain (S/D) metal 105 of the switching TFT and the S/D of the driving TFT (not shown in the drawings) are deposited to form a cross section diagram shown in FIG. 1-4; and
Then a protection layer (PVX layer) 106 is deposited to form a cross section diagram shown in FIG. 1-5; a via hole etching is conducted to expose the drain of the switching TFT and the gate of the driving TFT to form a cross section diagram shown in FIG. 1-6; an ITO (Indium Tin Oxide) layer 107 is deposited to form a cross section diagram shown in FIG. 1-7, thus achieving a jump layer connection of the switching TFT and the driving TFT.
Although the method can achieve a reliable connection of the jump layer of the switching TFT and the driving TFT, when splitting the GI layer of the Gate metal of the driving TFT, it needs to add a mask MASK on the FIG. 1-2. Splitting by using the masking process goes against cost saving and decreases fabrication efficiency.
Mode 2: The gate metals 101 of the switching TFT and the driving TFT are deposited on a glass substrate and are etched, and a GI layer 102 is deposited, to form a cross section diagram shown in FIG. 1-1;
An IGZO layer 103 is deposited at the position of the switching TFT on the GI layer 102. By etching the IGZO layer 103 by using wet etching, and depositing ESL layer 104 and etching , a cross section diagram shown in FIG. 1-2 is formed;
The source/drain (S/D) metal 105 of the switching TFT and the S/D of the driving TFT (not shown in the drawings) are deposited, and then a protection layer 106 is deposited, to form a cross section diagram shown in FIG. 2-1; a via hole etching is conducted, and by using different etching ratio of the atmosphere adopted by the dry etching process for the drain metal (such as the metal of MO), the GI layer (nano SiOx) and the protection layer (SiNx), under the precondition that the drain metal is assured not to be etched off, the GI layer on the gate metal of the driving TFT is completely etched off, and a via hole is formed, to form a cross section diagram shown in FIG. 2-2; and subsequently, an ITO layer 107 is deposited to form a cross section diagram shown in FIG. 2-3, thus achieving a jump layer connection of the switching TFT and a driving TFT.
Although the adoption of the method can reduce a sheet of MASK, it needs to regulate the dry etching process, increase the different etching ratios of the dry etching atmosphere for the metal of Mo, SiOx, and SiNx and increase complexity of the process.